1. Field of the Invention
The present invention generally relates to the fabrication of microfuses within a semiconductor structure and, more specifically, to a fuselink and process of fabricating a fuselink which is compatible with advanced CMOS technology having copper interconnections defined by a Damascene method and 2.5 volt circuitry, which fuselinks would be delectable either by a laser pulse or by a low voltage electrical pulse.
2. Description of Related Art
In the fabrication of integrated circuit (IC) structures, fusible links play an important role in improving the yield of the fabrication process. In general, it is desirable to provide redundancy in certain elements of the circuitry of an electronic component and the faulty element could be removed via a fuse and the component still be used. Two types of such fuses are in use. In one type, the fuse element is blown using an external heat source, e.g., laser beam. In a second type, the fuse is blown by flowing an electrical current through the fuse element. Electrical fuses are preferred as the fuse blow operation could be automated with a circuit test.
Three paramount requirements for a fuse are: a) material and process compatibility with thin film processes used to make the component; b) be capable of a clean blow meaning that a minimal amount of residue is left after the blow; and c) voltage compatibility with the circuitry used if an electrical blow is used.
The rapid increase of hand held IC devices has opened up a new world of low voltage circuitry for weight and power conservation. These type IC devices require a fuse which could be blown clean at or below 2.5 V. The low power circuitry also requires very high conductivity interconnection lines in the device. To meet this requirement, copper metallurgy is the preferred choice; which, in turn, mandates use of a Damascene process to make the device. Aluminum may also be employed to form the interconnection lines using known procedures.
In general, multilayer electronic components comprise multiple layers of a dielectric material having metallization on each layer in the form of vias, pads, straps connecting pads to vias and wiring. Vias or other openings in the dielectric layer extend from one layer to another layer. These openings are filled with a conductive material and electrically connect the metallization on one layer to the metallization on another layer and provide for the high density electronic components devices now used in industry.
An important aspect of multilayer electronic components is the via or openings between layers in which a conductive material is applied to provide electrical contact between the metallization on different layers. Broadly stated, the typical multilayer electronic component is built up from a number of layers of a dielectric material layer such as silicon oxide, fluorinated silicon oxide, polymers including polyimide and fluorinated polyimide, ceramics, carbon and other dielectric materials. In the processing sequence known in the art as the "Damascene Process", the dielectric layer is patterned using known techniques such as the use of a photoresist material which is exposed to define the wiring pattern. After developing, the photoresist acts as a mask through which a pattern of the dielectric material is removed by a subtractive etch process such as plasma etching or reactive ion etching. This is generally termed a lithography or photolithography process and may be used for both additive or subtractive metallization procedures as is known in the art.
Using the Damascene Process, openings defining wiring patterns are provided in the dielectric layer, extending from one surface of the dielectric layer to the other surface of the dielectric layer. These wiring patterns are then filled with a metallization metal using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination of methods. This process may include planarization of the metal on the surface of the dielectric by removing excess metallization with a method such as chemical mechanical polishing (CMP).
In the Single Damascene Process, vias or openings are additionally provided in the dielectric layer and filled with metallization to provide electrical contact between layers of wiring levels. In the Dual Damascene Process, the via openings and the wiring pattern openings are both provided in the dielectric layer before filling with metallization. This process simplifies the procedure and eliminates some internal interfaces. These procedures are continued for each layer in the electronic component until the electronic component is completed.
Various aspects of fuselinks in integrated circuits are described in U.S. Pat. Nos. 3,619,725 to Soden and Greig; 5,070,392 to Coffey and Hollingsworth; 5,185,291 to Fischer et al.; and 5,472,901 to Kapoor. Soden and Greig disclose a fuse structure comprising a thin film of titanium with or without a thin film of platinum, which is also the underlayer of titanium-platinum-gold interconnection lines used therein. The Ti--Pt--Au metallurgy typically suffers from resistance increase due to Pt and Au alloying. Further, platinum or gold is not compatible with the widely used aluminum interconnection metallurgy. In the Soden and Greig fuse, hundreds of miliamps of current is shown to be required to blow the fuse; such high current is not compatible with low voltage IC technologies. The fuse is also formed simultaneously with the interconnection circuit pattern.
Coffey and Hollingsworth also teach use of the underlayer of the interconnection line metallurgy as the fusible link. Coffey and Hollingsworth first form the interconnection line pattern and then remask to expose fusible link areas. The overlaying aluminum in these exposed areas is then chemically etched. This method is not applicable to copper metallurgy which requires a Damascene method. Further, Coffey and Hollingsworth profess use of a laser blow only.
Fischer et al. discloses a process where the thickness of interconnection lines is locally reduced to form the fuse link. Fischer et al. first deposit only half the required thickness of interconnection lines, photolithographically etch all of the metal where fuse links are to be formed, deposit other half thickness of metal and subtractively etch to form interconnection lines. Thus, the fuselinks are formed with half the thickness of metal lines. This method is not compatible with the current metallurgical schemes, all of which require an underlayer. Further, the interface formed between the top and the bottom half of the interconnection thickness is known to be preferred sites for void accumulation causing degraded reliability. Fischer's scheme is also incompatible with processes required for copper metallurgy.
Kapoor shows a method for integrating tungsten fuselinks with tungsten via studs. Fuselinks formed are in a picture frame shape which requires twice the current to blow the fuse because the current is divided into the two parallel branches. Further, the method is based upon the area dependence of polishing rate with higher polishing rate resulting in wider areas. This results in an inconsistent amount of tungsten being left along the sidewalls of the fuse recess resulting in poor fuse yield.
Carruthers et al. U.S. Pat. No. 5,340,775, assigned to the assignee of the present application, shows a method for making SiCr fuselinks integrated with aluminum metallurgy interconnection lines. To protect the SiCr fuselinks from harsh chemicals used for aluminum RIE, an overlayer of tungsten is used. This tungsten layer also forms an underlay for aluminum circuitry.
All the above patents are hereby incorporated by reference.
As cited above, the choice of fuse material in the prior art is often constrained to the material and process being used in the definition of interconnection lines. For example, an aluminum fuse in aluminum metallurgy, or use of the metallurgy of the barrier layer of interconnection lines etc. This results in use of a fuse thickness which is the same as that being used to define the interconnection lines. Such schemes necessarily make the desired electrical fuse blow techniques inoperable for many applications and one has to resort to a laser blow techniques. The reason for such fuse material constrains is erroneously said to be process simplicity or cost effectiveness. The laser blow operation, however, requires another mask application to remove the insulation layer above the fuse, requires expensive laser tools, adds logistics to keep track of which fuse in which chip is to be blown, and consumes more time than electrical fuse blow methods which could be automated with a device final test.
For a fuse to be electrically delectable at a low voltage, the role of various material properties, fuselink geometries, and electrical current requirement could be obtained from the following formula: ##EQU1## where, i, is the current required to blow the fuse; E.sub.f is the fusion energy of the use material;
.rho..sub.m is density of fuse material, PA1 A, is the cross-sectional area of the fuse link; and PA1 .rho..sub.e, is the electrical resistivity of the fuse material. PA1 forming a planarized surface comprising circuitry lines and surrounding internal insulation; PA1 depositing a thin layer of a fuse material on the planarized surface; PA1 defining the size and shape of the fuses and the circuitry connected by the fuses preferably using a photoresist; PA1 exposing the photoresist; PA1 developing the exposed photoresist; PA1 etching the exposed layer of fuse material; PA1 stripping the remaining photolithographic photoresist material; PA1 depositing at least one layer of final insulating and passivating material on the fuse defined planarized surface; PA1 forming, preferably by a damascene method, at least two via studs with each stud contacting circuitry linked by the fuse; and PA1 forming metal pads on the upper surface of the final insulating and passivating layer contacting the via studs.
For minimum fuse blow current one must choose a fuse material with low density, low fusion energy, and high electrical resistivity. The above equation shows that minimization of cross-sectional area of the fuselink has the strongest effect in reducing the fuse blow current. Further, the length of fuselink is not in the equation; hence, fuse length should be minimized as that would result in the highest available current for a given voltage.
Despite repeated efforts in the prior art, however, problems of poor fabrication process yield, process incompatibility, ability for clean electrical fuse blow, etc., remain and better methods for making reliable fuse links need to be developed.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for fabricating reliable, high process yield, microfuse links in semiconductor integrated circuit devices.
It is another object of the present invention to provide a method for fabricating integrated circuit fuse links, the method being compatible with copper metallurgy and the Damascene process.
A further object of the invention is to provide a fuselink in integrated circuit devices which is delectable by laser pulses or by electrical pulses.
It is yet another object of the present invention to provide a fuse in an integrated circuit device which could be electrically blown at below about 3.5 V, typically 1.5 V to 3 V.
It is another object of the present invention to provide an integrated circuit device article of manufacture containing fuses made using the method of the invention.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.